1. Field of the Invention
This invention relates generally to memory control systems for use in digital computing systems and, more particularly, but not by way of limitation, to an improved memory control system having an auto-incrementing address counter.
2. Prior Art Statement
In general, digital computing systems are provided with one or more memory subsystems, each of which provides access to a single data storage location of characteristic length in response to receiving an address of appropriate form from the central processing unit. In such systems, the central processing unit must supply additional addresses in order to access subsequent, sequential address locations in the memory. However, the effectiveness of relatively inexpensive PMOS ROM and dynamic RAM are substantially reduced when combined with the relatively higher speed monolithic, microprocessor devices currently available, primarily because of increased processor waiting time.